Integrated circuit field effect transistors are widely used in logic, memory, processor and other integrated circuit devices. As is well known to those having skill in the art, an integrated circuit field effect transistor includes spaced apart source and drain regions, a channel therebetween and a gate electrode adjacent the channel. Integrated circuit field effect transistors are often referred to as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply as MOS devices. Moreover, integrated circuit field effect transistors may be provided in two complementary types: N-channel field effect transistors, often referred to as N-MOS devices, and P-channel field effect transistors, often referred to as P-MOS devices. When both types of complementary transistor types are provided in a single integrated circuit, they may be referred to as CMOS devices. Although these terms will be used in the present application, they are used to generally denote integrated circuit field effect transistors and are not limited to field effect transistors having metal gates or oxide gate insulators.
As the integration density of integrated circuit field effect transistors continues to increase, the size of the active region and the channel length may continue to decrease. With the reduction in the channel length of the transistor, the influence of the source/drain upon the electric field or potential in the channel region may become considerable. This is called the “short channel effect”. Further, with the scaling down of the active size, the channel width decreases which may increase a threshold voltage. This is called the “narrow width effect”.
Various structures have been developed in attempts to improve or maximize the device performance, while reducing the sizes of elements formed on a substrate. For example, there are vertical transistor structures known as a fin structure, a DELTA (fully DEpleted Lean-channel TrAnsistor) structure and GAA (Gate All Around) structure.
For example, U.S. Pat. No. 6,413,802 discloses a FinFET device. As noted in the Abstract of this patent, a FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment, two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.
An example of a MOS transistor having DELTA structure is disclosed in U.S. Pat. No. 4,996,574. As noted in the Abstract of this patent, a metal-insulator-semiconductor transistor comprises an insulator layer, a semiconductor body provided on the insulator layer and comprising a source region, a drain region and a channel region extending in a first direction between and interconnecting the source region and the drain region, a gate insulator film provided on the semiconductor body so as to cover the channel region except for the part of the channel region in contact with the insulator layer, and a gate electrode of a conductive material provided in contact with the gate insulator film so as to cover the channel region underneath the gate insulator film except for the part of the channel region in contact with the insulator layer. The channel region has a width substantially smaller than twice the maximum extension of the depletion region formed in the channel region.
An example of a thin film transistor having the GAA structure is disclosed in U.S. Pat. No. 5,583,362. In typical MOS transistors of GAA structure, the SOI layer serves as an active pattern and a gate electrode is formed surrounding a channel region of the active pattern of which the surface is covered with a gate-insulating layer.
A field effect transistor having multiple stacked channels, and fabrication methods thereof, is described in application Ser. No. 10/610,607, filed Jul. 1, 2003, entitled Field Effect Transistors Having Multiple Stacked Channels, assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein. Integrated circuit field effect transistors are manufactured, according to some embodiments of application Ser. No. 10/610,607, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern comprises a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The plurality of interchannel layers are selectively removed to form a plurality of tunnels passing through the pre-active pattern, to thereby define an active channel pattern comprising the tunnels and a plurality of channels comprising the channel layers. A gate electrode is formed in the tunnels and surrounding the channels.